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[2017-12-05]

  数字集成电路  课程教学大纲

Course Outline

课程基本信息(Course Information

课程代码

Course Code

MR310

*学时

Credit Hours

68

*学分

Credits

4

*课程名称

Course Title

(中文)数字集成电路设计

(英文)Digital Integrated Circuit Design

*课程性质

Course Type

必修课

compulsory course

授课对象

Target Audience

           微电子科学与工程专业(本科生)本科2年级(Grade 2th)

*授课语言

(Language of Instruction)

                              中文(chinese

*开课院系

School

电院

先修课程

Prerequisite

基础电路理论、数字逻辑设计

(Electric Circuit, Digital Logic Design)

授课教师

Instructor

付宇卓

(FU yuzhuo)

课程网址

(Course Webpage)

http://cc.sjtu.edu.cn/portal/CC/Index.aspx

 

*课程简介(Description

(中文300-500字,含课程性质、主要教学内容、课程教学目标等)

本课程是电子工程、电子与计算机工程以及微电子工程专业的基础类课程,也可供有电路基础的计算机专业或相关电类专业本科生的选修课。教学目标包括:

l  知识体系

?    领会集成电路在晶体管层次的构成和工艺技术,了解深亚微米半导体平面工艺的特殊性和复杂性;

?    掌握集成电路的基本逻辑单元反向器的直流/交流电特性分析;

?    熟悉组合逻辑基本电路的各种类型和构成原理,能够运用简单的时延分析估算组合逻辑的时延;

?    熟悉运用逻辑努力的方法优化逻辑电路,包括非对称电路和高低扭斜电路优化问题;

?    掌握深亚微米工艺下线和互连所面临的问题,能够使用经典Elmore模型分析互连线的RC效应;

?    了解时序逻辑的基本分类和构成;

?    掌握基本时序电路的构成原理和时序约束,能分析各种类型动态、静态锁存器和触发器的电路原理和特征;

?    掌握加法器的各种设计原理,能否运用PG图分析复杂加法器的构成

l  能力

?    熟练使用SPICE等工具进行晶体管层次仿真;

?    学习Cadence工具的使用技能;

?    了解数字集成电路相关技术的国际期刊,训练基本的文献阅读能力,收集当前数字集成电路产业领域的新技术

?    专业技术的表达能力

*课程简介(Description

 

DIC is one of the fundamental course for Electric Engineerign,Electric and Computer Engineering, Microelectronic Engineering. Also could be learned as selective course for related majors. Teaching target includes

l  Knowledge level

?    Knowledge in transistor level including structure and processing technology, understand those Deep-Submicron processing technology.

?    DC/AC characteristic analysis of CMOS inverter.

?    Static CMOS layout tricky, VTC data dependency,propagate delay definitions,RC model,Static CMOS size,fan-in/fan-out tech.,Logic effort,CMOS power analysis

?    Numeric logical effort characterizes gates,NANDs are faster than NORs in CMOS,Paths are fastest when effort delays are ~4,Path delay is weakly sensitive to stages, sizes.Using fewer stages doesn’t mean faster paths.Delay of path is about log4H stage

?    Knowledge about deep submicron wire and interconnect issues, analysis interconnect wire using elmore model

?    Sequential logic including Timing,Static Latches and Registers,Dynamic Latches and Registers

?    1-Bit full adder structure and complicated adder architecture using PG graph.

l  Ability level

?    Transistor level simulation using SPICE tool

?    Using cadence tool for layout

?    Review the advanced technology through electric journal and library

?    Technical communication

课程教学大纲(course syllabus

*学习目标(Learning Outcomes)

基础性

从集成电路器件、反向器、组合逻辑、互联的电路级建模、分析到设计、了解时序电路和算术电路的晶体管级分析和设计。

工程技能训练

运用版图工具的基本设计技能、SPICE的电路分析能力

前沿性包含

未来集成电路设计所面临的Wire 问题、存储器带宽问题,3D IC的热点研究领域

*教学内容、进度安排及要求

(Class Schedule

&Requirements)

No.

Topic

hours

Contents

Comments

1

Chapter1-History of IC

2

History of IC

Moore’s law

China IC Industry

 

Chapter1-Fundamental background 1

2

Bottom-up such as

Device physics

Gate

 

2

Chapter1-Fundamental background 2

2

DIC characteristic

 

Chapter1-Fundamental background 3

2

Logic Flip-flop

Layout fundemental

 

3

Chapter1-CMOS Processing/layout

2

CMOS processing

 

Chapter2-CMOS transistor device

modeling

2

CMOS transistor introduction

Ideal I-V characteristics under static conditions

Velocity Saturation

 

4

Chapter2-CMOS transistor device

modeling

2

Dynamic Characteristics

Nonideal I-V effects

Handing HW1

Chapter2-CMOS transistor device

modeling

2

Dynamic Characteristics

Nonideal I-V effects

 

5

Chapter3-CMOS inverter

Static behavior(1)

2

CMOS inverter at a glance

NMOS inverter,TTL inverter

CMOS interver static behavior

Handing HW2

Chapter3-CMOS inverter

Static behavior(2)

2

CMOS interver static behavior

 Lab1HSPICE/Unix using/layout

6

Workshop1

2

How to Test for IC

 

Chapter3-CMOS inverter

Dynamic behavior(1)

2

CMOS dynamic behavior

Capacitor computing

 

7

Chapter3-CMOS inverter

Dynamic behavior(2)

2

Inverter chain computing

 

8

Chapter3-CMOS inverter

Power analysis

2

Power, Energy, and Energy

Delay

Perspective tech.

Quiz1

SPICE+Exercise Review

 

1+1

SPICE introduction

Exercise Review

Workshop Review1

 Exercise class1

9

Chapter4-

CMOS combinational fundamental

2

CMOS static characteristic

CMOS propagate delay

Large fan-in technology

 

Chapter4-logic effect1

2

Introduction

Delay in a Logic Gate

Multistage Logic Networks

Lab2:CMOS inverter Chain

10

Chapter4-logic effect2

2

Choosing the Best Number of Stages

Example

Summary

define topic3

 

Chapter4-

CMOS combinational ratio-logic

2

Basic concept

Resistive load

Depletion NMOS

Pseudo NMOS

DCVSL logic

Pseudo NMOS logic effort

Handing HW3

11

Chapter4-CMOS dynamic logic

1+1

Dynamic logic principle

Dynamic logic properties

Dynamic logic design issues

Dynamic logic cascade solution

Exercise class3

 

2

Mid Exam

 

12

Chapter5-Datapath adder

 fundamental

2

Full adder various circuit implementation

Manchester Carry Chain

P/G rule

Handing HW4/define workshop topic2

Chapter5-Datapath adder various

 architecture

2

Carry-Ripple Adder

Carry-Skip Adder

Carry-Lookahead Adder

Carry-Select Adder

Carry-Increment Adder

Tree Adder

 

13

Chapter5-Datapath multiplication

2

Unsigned multiplication

Complementation multiplication

Wallace tree

Booth encoder

Serial multiplication

 Lab.combinational 4-bit adder design

Workshop2

1+1

 Low Power Tech.

Exercise class4

14

Chapter6- wire

2

Wire Capacitance

Wire Resistor

Wire crosstalk issue

Elmore module

Handing HW5

Chapter7- Sequential Circuit

timing

2

Timing definition

Min&Max Constrain

Time borrow&Time Skew

Handing HW6

15

Chapter7-Sequential Circuit

static latch&Registers

2

Latch circuit principle

FF circuit principle

Various static FF design

(reset/rest)

Quitz3

Chapter7-Sequential Circuit

dynamic latch&Registers

2

Dynamic FF principle

Various static FF design

Quiz4(datapath)

 

16

Chapter8-memory

2

SRAM general structure

 

Handing HW7

Review/exercise class5

1+1

 Workshop Review2

Exercise class5

17

Q&A

 

 

 Hand Lab1-3

Q&A

 

Final exam

 

*考核方式

(Grading)

(成绩构成)

作业

实验报告

文献报告

评价报告递交

考试

测验

期中考试

期末考试

6*4

4*4

2*4

1*4

4*2

20

22

 

 

*教材或参考资料

(Textbooks & Other Materials)

?     Digital integrated circuit Jan M.Rabaey

?     CMOS VLSI design- a circuits and systems perspective Meil H.E.Weste, addison wesley press

?      “Computer organization and design” John.l.hennessy

?     “CMOS IC layout”, dan clein

?     “Reuse Methodology manual for system-on-chip designs”, Michael Keating

?     “Microelectronic Circuits:Analysis and Design” Muhammad H.Rashid

 

其它

More

 

备注

Notes

 

 

备注说明:

1.带*内容为必填项。

2.课程简介字数为300-500字;课程大纲以表述清楚教学安排为宜,字数不限。

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